1. Field of the Invention
The present invention relates to a method of forming a fine pattern of a semiconductor device. More particularly, the present invention relates to using double patterning to form a layout of a semiconductor device having a fine pattern.
2. Description of the Related Art
Circuit patterns in highly integrated semiconductor devices must be especially fine to accommodate the circuit layouts. In other words, individual unit devices must be small in order to incorporate several such unit devices in a limited space. Accordingly, the pitch of a semiconductor pattern (i.e., the sum of the widths and gaps of the patterns to be formed) must be minimized. However, as a practical matter, formation of patterns having fine pitches is limited by the resolution capabilities of the photolithography process used to form the patterns, such as the line and space patterns, of the semiconductor device. In other words, the higher the resolution of the photolithography process, the finer the formation of the pattern.
A double patterning process addresses, to some extent, resolution limitations of the photolithography process for forming fine patterns. According to this process, first line patterns are formed using exposing and developing processes, while second line patterns are formed among the first line patterns relying on the semiconductor fabrication process.
However, when lines and other features of the first line patterns are cut or separated, by design or during the fabrication process, a second pattern layer may be deposited in the gaps between the severed portions of first line pattern. As a result, portions of the second line pattern may unintentionally be connected (or short-circuited) to one another. This connection may require an additional trimming process to separate the connected portions of the second line pattern. Such a trimming process complicates the fabricating process and reduces economic efficiency.